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| SEMICONDUCTOR CD74HC139, CD74HCT139 High Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer Description The Harris CD74HC139, CD74HCT139 contain two independent binary to one of four decoders each with a single active low enable input (1E or 2E). Data on the select inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four normally high outputs to go low. If the enable input is high all four outputs remain high. For demultiplexer operation the enable input is the data input. The enable input also functions as a chip select when these devices are cascaded. This device is functionally the same as the CD4556B and is pin compatible with it. The outputs of these devices can drive 10 low power Schottky TTL equivalent loads. The 74HCT logic family is functionally as well as pin equivalent to the 74LS logic family. September 1997 Features * Multifunction Capability - Binary to 1 of 4 Decoders or 1 to 4 Line Demultiplexer * Active Low Mutually Exclusive Outputs * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH * Memory Decoding, Data Routing, Code Conversion Ordering Information PART NUMBER CD74HC139E CD74HCT139E CD74HC139M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC PKG. NO. E16.3 E16.3 M16.15 Pinout CD74HC139, CD74HCT139 (PDIP, SOIC) TOP VIEW 1E 1 1A0 2 1A1 3 1Y0 4 1Y1 5 1Y2 6 1Y3 7 GND 8 16 VCC 15 2E 14 2A0 13 2A1 12 2Y0 11 2Y1 10 2Y2 9 2Y3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 File Number 1545.1 1 CD74HC139, CD74HCT139 Functional Diagram 4 (12) 2 (14) A0 3 (13) A1 5 (11) Y1 6 (10) Y2 7 (9) 1 (15) E Y3 Y0 TRUTH TABLE INPUTS ENABLE SELECT E 0 0 0 0 1 A1 0 0 1 1 X A0 0 1 0 1 X Y3 1 1 1 0 1 OUTPUTS Y2 1 1 0 1 1 Y1 1 0 1 1 1 Y0 0 1 1 1 1 NOTE: X = Don't Care, Logic 1 = High, Logic 0 = Low Logic Diagram 4 (12) Y0 5 (11) Y1 3 (13) A1 6 (10) Y2 7 (9) Y3 2 (14) A0 1 (15) E 2 CD74HC139, CD74HCT139 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA Thermal Information Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS 3 CD74HC139, CD74HCT139 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS VCC (V) -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 0 0 - 5.5 5.5 4.5 to 5.5 100 0.1 8 360 - 1 80 450 - 1 160 490 A A A HCT Input Loading Table INPUT All UNIT LOADS 0.7 NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360A max at 25oC. Switching Specifications Input tr, tf = 6ns TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS PARAMETER HC TYPES Propagation Delay A0, A1 to Outputs SYMBOL tPLH, tPHL CL = 50pF 2 4.5 6 - 12 11 145 29 25 135 27 23 - - 180 36 31 170 34 29 - - 220 44 38 205 41 35 - ns ns ns ns ns ns ns ns E to Outputs tPLH, tPHL CL = 50pF 2 4.5 6 Select to Output Enable to Output tPLH, tPHL tPLH, tPHL CL = 15pF CL = 15pF 5 5 4 CD74HC139, CD74HCT139 Switching Specifications Input tr, tf = 6ns (Continued) 25oC MIN TYP 55 MAX 75 15 13 10 -40oC TO 85oC MIN MAX 95 19 16 10 -55oC TO 125oC MIN MAX 110 22 19 10 UNITS ns ns ns pF pF PARAMETER SYMBOL TEST CONDITIONS CL = 50pF VCC (V) 2 4.5 6 Output Transition Time (Figure 1) tTLH, tTHL Power Dissipation Capacitance, (Notes 5, 6) Input Capacitance HCT TYPES Propagation Delay A0, A1 to Outputs E to Outputs Select to Output Enable to Output Output Transition Time (Figure 2) Power Dissipation Capacitance, (Notes 5, 6) Input Capacitance NOTES: CPD CIN - 5 - tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL CPD CIN CL = 50pF CL = 50pF CL = 15pF CL = 15pF CL = 50pF - 4.5 4.5 5 5 4.5 5 - - 14 14 59 - 34 34 15 10 - 43 43 19 10 - 51 51 22 10 ns ns ns ns ns pF pF 5. CPD is used to determine the dynamic power consumption, per decoder/demux. 6. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V GND tTHL INVERTING OUTPUT FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5 |
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